Here is an opportunity for only those having flair for technical excellence in analog/Mixed Signal IC Design, Analog/Mixed Signal IC Characterization and IC layout domains.

Applications are invited for the following job positions from well motivated and experienced design engineers to work in our consortium companies.

Candidates are requested to send their profiles by attaching their latest resume to hr@vedaiit.com on or before December 10, 2008.

Analog/ Mixed Signal IC Design Engineer:

 Responsibilities In this position: 

You will be responsible for the development of analog/mixed-signal/memory/standard cell designs. You will participate in all aspects of the design including specification, architectural development, transistor level design, layout supervision, chip level verification, and lab validation.   

 Qualifications include: 

·     Strong knowledge of analog design fundamentals 

·     Discrete time and continuous time signal processing skills   

·     Expert knowledge in Data converter/IO/PLL design     

·     Transistor and system level simulation skills

·     Strong lab and silicon validation skills

·     Strong written and verbal communication skills

·     Proven experience taking designs from concept to tape out and then silicon debug support, yield improvement support etc. 

Educational and Professional Requirements: 

Candidates must possess a Bachelor's or Master's or Doctorate degree in EEE/ECE and 4+ years of professional experience in mixed signal CMOS circuit design.

 Candidates for the Lead Engineer should have: 

The candidate will be required to design in a variety of technologies (CMOS or BICMOS) and must have demonstrated the ability to design the following: High Speed ADC, High Speed DAC, PLL, and Continuous-Time Filters. The individual will be responsible for all activities from concept, to design, implementation, and validation/debugging. The Candidate will be working on state of the art technology and design implementation. Candidate will be required to guide technically other team members in their daily activities.  This implies a facility to communicate crisply his /her technical ideas and knowledge.

Analog/ Mixed Signal IC Characterization Engineer:

 Description

You will be responsible for the characterization of mixed signal IPs  which are either standalone analog IC chips or SoCs in which these IPs are embedded. A good knowledge of various performance criteria of analog blocks is very important. Familiarity with various lab equipment – like oscilloscopes, data acquisition systems is very much desired.

 Required Abilities:

 Mixed-signal IP characterization requires

·         Familiarity with performance metrics for various analog IPs

·         Familiarity in using Lab equipments

·         programming,

·         excellent written and oral communications,

·         status reporting and statistical analysis.

 Essential Duties:

 Define, develop, implement and characterization plans for analog IPs.

·     Maintain and expand skills for semiconductor characterization methodologies and military standards.

·     Support operations in the test and burn-in of analog and mixed-signal devices.

·     Design and develop test hardware (probe cards and fixture boards.) whenever required

·     Define, select, purchase, install and qualify new test equipment.

·     Assist in the debug of semiconductor designs.

·     Develop tools and procedures to reduce time to market and improve quality.

Educational and Professional Requirements: 

Candidates must possess a Bachelor's or Master's or Doctorate degree in ECE/EEE with 2 to 4 years of professional experience in Mixed Signal IC Characterization. However people with polytechnic diploma and good professional experience are also eligible to apply.

IC Layout Design Engineer:

 Description

You will be a member of a team responsible for the development of layouts for various kinds of analog/mixed-signal/memory/standard cell designs in different process geometries.
Duties include:

·     Providing support, training and mentoring where required for less experienced members of the layout team.

·     Definition and/or implementation department-wide tools and strategies

·     To act as a point of technical reference. 

·     To review layout timescales prior to agreement with project leader

·     Generating layout to the satisfaction of the project Design Lead.

·     IC floor planning, conversion of analog and digital circuit schematics into efficient layouts that meet device requirements, whilst conducting schematic verification and design-rule verification using high performance CMOS process technologies. 

You will be responsible for the layout and verification of designs such as, but not limited to, amplifiers, ADCs, SRAMs, Digital Custom Macros, band gap references, oscillators, high voltage circuits large power arrays and the chip top level.

The successful candidate will take ownership of all aspects of the layout process to insure successful implementation to the product schedule.

Educational and Professional Requirements: 

Candidates must possess a Bachelor's or Master's or Doctorate degree in engineering/science with 1 to 4 years of professional experience in Analog/Custom Layout Design. However people with polytechnic diploma and good professional experience are also eligible to apply

Candidates for the Lead Engineer should have:

·     Be capable of handling complex chips concurrently.

·     Proven track record of on-time delivery.

·     Capable of laying out power output cells, Charge Pumps etc

·     Able to create scripts as required

·     To act as technical advisor on floorplans i.E. Pad ring, ESD, signal, bus and power routing strategies.

·     Responsible for the training, mentoring and performance reviews of less experienced layout staff.

·     Understanding of standard CMOS process topologies, theory and principals of analog CMOS layout, cross-coupling, interdigitation, and other matching techniques.